As the demands of technology require smaller and more powerful electronic devices, there is a need for semiconductors with increased performance. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, new methods for improving performance without scaling have become critically important.
One approach for improving semiconductor performance is to increase carrier (electron and/or hole) mobilities. Increased carrier mobility can be obtained, for example, by introducing an appropriate strain into the Si lattice of the silicon (Si)-containing substrate that is used to fabricate the semiconductor device into the finished product of an integrated circuit.
The application of stress along the channel changes the lattice dimensions of the silicon (Si)-containing substrate that is used to fabricate the semiconductor device. By changing the lattice dimensions, the band structure and mobility of the material are changed as well. These stresses are induced using a stress film. The stress film is typically a nitride liner, such as Si.sub.3N.sub.4. These stress films are known in the semiconductor industry. For example, U.S. published patent application US20050258515 entitled “Embedded Stressed Nitride Liners for CMOS Performance Improvement,” which is incorporated in its entirety herein by reference, discloses such a stress film. The stress in applied to a channel can be increased when the stress nitride is moved close to the channel. This technique is generally known in the industry as a “Stress Proximity Technique” (SPT).
Compressive longitudinal stress along the channel of a field effect transistor (FET) increases drive current in p-type field effect transistors (PFET) and decreases drive current in n-type field effect transistors (NFET). Tensile longitudinal stress along the channel of a field effect transistor (FET) increases drive current in NFETs and decreases drive current in PFETs.
One method of executing the SPT involves removing spacers surrounding the gate of the FET in order to bring the stress film closer to the device channel without etching existing films on the device structure. One problem with this method is that devices that are not targeted for SPT also lose their spacers, and are thereby degraded.
Another method is to relax the stress film only on the non-targeted devices. However, this requires an additional lithography level and implant process. Furthermore, it is difficult to completely relax the stress film. Furthermore, due to the non-uniform nature of the stress film (where it is thinner on surfaces parallel to the direction of deposition, and thicker on surfaces perpendicular to the direction of deposition), the relaxing species can easily penetrate the film where protection is most needed, thereby degrading the semiconductor device.
Therefore, what is needed is an improved method for efficiently executing an SPT process, without adding undue manufacturing complexity.